There are several application areas where on-chip charge transport in interconnect has become a severe problem. The more the feature sizes are reduced in integrated circuits (such feature size reduction is required in frame-transfer charge-coupled device (CCD) image sensors suitable for HDTV for example) the larger the RC-values. This puts severe challenges on the technology in which the IC is manufactured. Several improvements in the technology have been reported in order to tackle the problem of increasing RC-values.
For instance, H. L. Peek et al. “Groove-fill of tungsten and poly-Si membrane technology for high performance (HDTV) FT-CCD imagers”, Proceedings of IEDM 93, p. 567-570, discloses several technology enabling the manufacturing of a HDTV Frame Transfer CCD sensor, being: 1) a groove-fill titanium-tungsten/tungsten shunt wiring technology, directly resulting in a planar surface; 2) non-overlapping poly-Si transfer gate method, and 3) very thin poly-Si gate-electrodes (membrane poly-gates technology). It is further disclosed that with these technologies a high-vertical frame-shift frequency of 2.5 MHz, a low-on-chip power dissipation of 560 mW, and a high sensitivity in general (especially in blue) has been fabricated successfully.
Nevertheless, the shunt-wiring technology as described above has faced its limits, and the charge transport speed still appeared to be a problem, because of the resistance of Tungsten wires and the increase in resolution and speed requirements of large CCD's for Photogrammetry and Professional Photography.
U.S. Pat. No. 5,504,355 reports a solid stage image sensor device having an effective light detecting element and a peripheral circuit including a light shielding firm for shielding a periphery of the effective light detecting element, a first wiring film made of the same material as that of the light-shielding film and formed in the same process as that for the light-light-shielding film, and a second wiring film of aluminum for the peripheral circuit. The first wiring film and the second wiring film form a two-layer wiring structure of the peripheral circuit and are electrically interconnected through contact holes in an interlayer insulating film. With this arrangement, it is possible to lower the wiring resistance for the peripheral circuit and also to cause a signal transfer clock pulse of high-frequency to propagate without its waveform becoming dull.
KR20020059120A discloses a fabrication method of a CMOS image sensor, which is provided to minimize a contact resistance during metallization by maintaining a uniform contact resistance to each pixel. After forming a BPSG layer on a semiconductor substrate, a contact hole is formed by selectively etching the BPSG layer. An adhesive layer is formed on the resultant structure. A tungsten film and an aluminum metal wire are sequentially formed by CVD (chemical vapor deposition) so as to fill the contact hole.